Custom RISC-V CPU ISA Compliance

A Bangalore-based fabless semiconductor startup had designed a 64-bit RISC-V application processor targeting edge AI inference and embedded Linux workloads. The processor implemented the RV64GC base ISA (RV64I + M + A + F + D + C extensions) as defined in the RISC-V Unprivileged ISA Specification v20191213 (Waterman & Asanović, RISC-V Foundation, 2019) and the RISC-V Privileged Architecture Specification v20211203.

Beyond the ratified base ISA, the team had developed three proprietary extensions: a SIMD vector DSP extension for 8-bit MAC operations (targeting neural network inference), a custom cryptographic extension implementing AES-128/256 and SHA-256 in hardware, and a memory-tagging extension for hardware-enforced memory safety — a technique gaining traction following ARM's Memory Tagging Extension (MTE) introduction in ARMv8.5-A (ARM Architecture Reference Manual, 2021).

The client required RISC-V International compliance certification to access the commercial IP licensing ecosystem and to satisfy due diligence requirements from Series A investors. Compliance failures discovered post-silicon would have required a costly re-spin estimated at USD 2–4 million on their target 28 nm process node.

RISC-V Architectural Compliance Tests (RISCV-ACT): SNS executed the complete RISC-V International Architectural Compatibility Test (ACT) suite — the official compliance framework maintained at github.com/riscv-non-isa/riscv-arch-test. The suite comprised 4,800+ directed assembly tests covering all RV64GC instructions, privilege modes (M/S/U), exception handling, and CSR behaviour. Each test compares processor output against a golden reference signature generated by the Spike RISC-V ISA simulator.

RISC-V Formal Interface (RVFI) + Formal ISA Checking: The processor's RTL was instrumented with the RISC-V Formal Interface (RVFI) — a standardised trace interface defined by Clifford Wolf (SymbiYosys, 2018) — enabling formal ISA checking using the riscv-formal framework. This approach exhaustively verifies that every instruction's architectural state update matches the ISA specification, catching subtle pipeline hazard bugs that simulation-based approaches miss. Ninety-five formal properties were proven, covering all instruction classes and exception scenarios.

Custom Extension Verification: For the three proprietary extensions, SNS authored a custom compliance test suite following the RISC-V non-ISA specification process (RISC-V International, 2022). The DSP extension was validated against the RISC-V "P" extension draft specification and IEEE 754-2019 for floating-point semantics. The cryptographic extension was verified against NIST FIPS 197 (AES) and NIST FIPS 180-4 (SHA-256) test vectors — the definitive standards for these algorithms. The memory-tagging extension was validated against a formal model derived from the CHERI capability architecture research (Watson et al., An Introduction to CHERI, University of Cambridge TR-941, 2019).

Privileged Architecture Compliance: Machine-mode (M), Supervisor-mode (S), and User-mode (U) privilege transitions, Physical Memory Protection (PMP), and Virtual Memory (Sv39/Sv48) were verified using a combination of directed tests and the RISC-V Privileged Architecture Test Suite. Linux kernel boot (v6.1 LTS) on the RTL simulation was used as an integration-level compliance check, validating the complete privileged software stack.

The engagement achieved 100% pass rate on all 4,800+ RISC-V ACT compliance tests across RV64GC. All 95 formal RVFI properties were proven. The three custom extensions were fully validated against their respective specifications and NIST test vectors.

Nine RTL bugs were discovered: 2 critical ISA compliance violations (incorrect exception delegation in S-mode), 4 major (CSR read-modify-write atomicity violations), and 3 minor (performance counter overflow edge cases). All were resolved before tape-out.

The client successfully obtained RISC-V International compliance certification, enabling them to market the processor as a certified RISC-V implementation. The processor subsequently booted Linux 6.1 LTS in silicon first-pass, with all three custom extensions functional. The startup closed their Series A funding round within 60 days of tape-out, citing the compliance certification as a key investor confidence factor.