Chiplet Interface Verification

The chiplet paradigm — disaggregating a monolithic SoC into multiple smaller dies integrated in a single package — has emerged as the dominant scaling strategy as Moore's Law slows. Intel's Ponte Vecchio GPU (2022) integrates 47 active tiles; AMD's EPYC Genoa (2022) uses 13 chiplets. The global chiplet market is projected to reach USD 58.2 billion by 2030 (Allied Market Research, 2023), driven by heterogeneous integration of compute, memory, and I/O dies.

The client — a fabless design house — was building a data centre accelerator using 2.5D integration: a compute die (custom RISC-V + ML accelerator), an HBM2E memory die, a PCIe 5.0 / CXL 2.0 I/O die, and a security/root-of-trust die, all interconnected via the Universal Chiplet Interconnect Express (UCIe) standard on a silicon interposer.

UCIe 1.0 was published by the UCIe Consortium in March 2022 (founding members: Intel, AMD, ARM, TSMC, Samsung, ASML, and others), with UCIe 1.1 released in April 2023 adding enhanced FDI (Flit-aware Die-to-Die Interface) capabilities. The standard defines three layers: Physical Layer, Die-to-Die Adapter (D2D), and Protocol Layer (supporting PCIe and CXL protocols). Verifying all three layers across four chiplets with correct inter-die credit management, link training, and error recovery presented a verification challenge of unprecedented complexity for the client's team.

UCIe Protocol VIP Development: SNS developed a custom UCIe 1.1 Verification IP (VIP) in SystemVerilog UVM, implementing all three protocol layers as defined in the UCIe 1.1 specification. The VIP included a full UCIe Physical Layer model (supporting both Advanced and Standard package options), a D2D Adapter model with credit-based flow control, and Protocol Layer models for both PCIe 5.0 and CXL 2.0 flit formats. This approach follows the methodology described by Salewski & Timmermann in Protocol Verification of On-Chip Interconnects (IEEE SOCC 2019).

Multi-Die System Simulation: All four chiplet RTLs were co-simulated in a single UVM testbench environment — a technically demanding setup requiring careful management of simulation performance. SNS employed hierarchical simulation partitioning and incremental compilation to maintain simulation throughput above 10 MHz effective clock rate, enabling execution of 3,200+ protocol-level test cases within the project timeline.

Link Training & Initialization Verification: UCIe link training involves a multi-phase initialization sequence (Reset → Detect → Polling → Configuration → Active) with complex handshake protocols between dies. SNS authored 340 directed tests specifically targeting link training corner cases: asymmetric lane widths, clock domain crossing (CDC) violations, and error recovery from link training failures. CDC analysis was performed using formal CDC checking tools, identifying 7 potential metastability paths that were resolved before sign-off.

CXL 2.0 Protocol Compliance: The I/O die's CXL 2.0 implementation was verified against the CXL Consortium specification v2.0 (2020), covering CXL.io (PCIe-based), CXL.cache (host-device cache coherency), and CXL.mem (host-managed device memory) sub-protocols. Compliance testing followed the CXL Consortium's Compliance Test Specification, with all mandatory test cases executed and passed.

Power-Aware Verification: UCIe defines power management states (L0, L0p, L1, L2) with specific latency and bandwidth requirements. SNS verified all power state transitions and wake-up sequences, ensuring compliance with the UCIe 1.1 power management requirements — a critical requirement for data centre applications where power efficiency directly impacts total cost of ownership.

The engagement achieved full UCIe 1.1 compliance across all three protocol layers for all four chiplets. All 3,200+ protocol test cases passed. Zero interoperability escapes were found post-silicon — the 4-chiplet system achieved first-pass inter-die communication at bring-up.

Seventeen RTL bugs were discovered: 5 critical (credit counter overflow causing deadlock under sustained traffic), 8 major (incorrect CXL.cache snoop response ordering), and 4 minor (power state transition timing violations). The 5 critical deadlock bugs would have been extremely difficult to reproduce post-silicon and could have required a full re-spin.

The client's accelerator achieved UCIe Consortium interoperability certification, enabling them to market the device as UCIe-compliant and participate in the growing chiplet ecosystem. Measured inter-die bandwidth at bring-up was 512 GB/s (matching the RTL performance model), with link latency of 8 ns — within 5% of the specification target.